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differential-to-lvds/0.7v differential pci express? jitter attenuator ics8741004i idt? / ics? pci express? jitter attenuator 1 ics8741004bgi rev. a may 29, 2008 general description the ics8741004i is a high performance differential-to-lvds/0.7v differential jitter attenuator designed for use in pci express? systems. in some pci ex press systems, such as those found in desktop pcs, the pci express clocks are generated from a low bandwidth, high phase noise pll frequency synthesizer. in these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the pll synthesizer and from the system board. the ics8741004i has 3 pll bandwidth modes: 200khz, 600khz and 2mhz. the 200khz mode will provide maximum jitter attenuation, but with higher pll tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. the 600khz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. the 2mhz bandwidth provides the best tracking skew and will pass most spread prof iles, but the jitter attenuation will not be as good as the lower bandwidth modes. because some 2.5gb serdes have x20 multipliers while others have x25 multipliers, the ics8741004i can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100mhz input/125mhz output) using the f_sel pins. the ics8741004i uses idt?s 3 rd generation femtoclock? pll technology to achieve the lowest possible phase noise. the device is packaged in a 24 lead tssop package, making it ideal for use in space constrained applications such as pci express add-in cards. pll bandwidth features ? two lvds and two 0.7v differential output pairs bank a has two lvds output pairs and bank b has two 0.7v differential output pairs ? one differential clock input pair ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? output frequency range: 98mhz - 160mhz ? input frequency range: 98mhz - 128mhz ? vco range: 490mhz - 640mhz ? cycle-to-cycle jitter: 35ps (maximum) ? full 3.3v operating supply ? three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages pin assignment 24-lead tssop, e-pad 4.40mm x 7.8mm x 0.925mm package body g package top view bw_sel 0 = pll bandwidth: ~200khz float = pll bandwidth: ~600khz (default) 1 = pll bandwidth: ~2mhz hiperclocks? ic s 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nqa1 qa1 v ddo qa0 nqa0 mr bw_sel nc v dda f_sela v dd oea nqb1 qb1 v ddo qb0 nqb0 iref f_selb oeb gnd gnd nclk clk
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 2 ics8741004bgi rev. a may 29, 2008 block diagram f_sela 0 5 (default) 1 4 f_selb 0 5 (default) 1 4 vco 490 - 640 mhz phase detector m = 5 (fixed) qa0 nqa0 qa1 nqa1 pullup pullup pulldown float pulldown oea oeb f_sela f_selb bw_sel clk nclk mr iref pullup pulldown pulldown qb0 nqb0 qb1 nqb1 0 = ~200khz float = ~400khz 1 = ~800khz
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 3 ics8741004bgi rev. a may 29, 2008 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 nqa1, qa1 output differential ou tput pair. lvds interface levels. 3, 22 v ddo power output supply pins. 4, 5 qa0, nqa0 output differential outp ut pair. lvds interface levels. 6 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs q[ax:bx] to go low and the inverted outputs nq[ax:bx] to go high. when logic low, the internal dividers and the outputs are enabled. lvcmos/lvttl interface levels. 7 bw_sel input pullup/ pulldown pll bandwidth input. lvcmos/lvttl interface levels. see table 3b. 8 nc unused no connect. 9v dda power analog supply pin. 10 f_sela input pulldown frequency select pins for qax/nqax outputs. lvcmos/lvttl interface levels. see table 3c. 11 v dd power core supply pin. 12 oea input pullup output enable for qax pins. when high, qax/nqax outputs are enabled. when low, the qax/nqax outputs are in a high impedance state. lvcmos/lvttl interface levels. see table 3a. 13 clk input pulldown non-inverting differential clock input. 14 nclk input pullup inverting differential clock input. 15, 16 gnd power power supply ground. 17 oeb input pullup output enable for qbx pins. when high, qbx/nqbx outputs are enabled. when low, the qbx/nqbx outputs are in a high impedance state. lvcmos/lvttl interface levels. see table 3a. 18 f_selb input pulldown frequency select pins for qbx/nqbx outputs. lvcmos/lvttl interface levels. see table 3c. 19 iref input a fixed precision resistor (rref = 475 ? ) from this pin to ground provides a reference current used for differentia l current-mode qb0/nqb0 clock outputs. 20, 21 nqb0, qb0 output differential ou tput pair. hcsl interface levels. 23, 24 qb1, nqb1 output differential ou tput pair. hcsl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 4 ics8741004bgi rev. a may 29, 2008 function tables table 3a. output enable function table table 3c. frequency select table table 3b. pll bandwidth function table absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c inputs outputs oea oeb qa[0:1]/nqa[0:1] qb[0:1]/nqb[0:1] 0 0 hi-z hi-z 1 1 enabled enabled inputs divider f_sel[a, b] 0 5 (default) 14 input pll bandwidth bw_sel 0 ~200khz float ~600khz (default) 1~2mhz item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 32.1 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.12 3.3 v dd v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 45 ma i dda analog supply current 12 ma i ddo output supply current 80 ma
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 5 ics8741004bgi rev. a may 29, 2008 table 4b. lvcmos/lvttl dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c table 4c. differential dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . table 4d. lvds dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage oea, oeb, mr, f_sela, f_selb 2v dd + 0.3 v bw_sel v dd ? 0.3 v dd + 0.3 v v il input low voltage oea, oeb, mr, f_sela, f_selb -0.3 0.8 v bw_sel -0.3 +0.3 v v im input mid voltage bw_sel v dd /2 ? 0.1 v dd /2 + 0.1 v i ih input high current f_sela, f_selb, mr, bw_sel v dd = v in = 3.465v 150 a oea, oeb v dd = v in = 3.465v 5 a i il input low current mr, f_sela, f_selb, v dd = 3.465v, v in = 0v -5 a oea, oeb, bw_sel v dd = 3.465v, v in = 0v -150 a symbol parameter test conditio ns minimum typical maximum units i ih input high current clk v dd = v in = 3.465v 150 a nclk v dd = v in = 3.465v 5 a i il input low current clk v dd = 3.465v, v in = 0v -5 a nclk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, note 2 gnd + 0.5 v dd ? 0.85 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 290 390 490 mv ? v od v od magnitude change 50 mv v os offset voltage 1.2 1.35 1.5 v ? v os v os magnitude change 50 mv
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 6 ics8741004bgi rev. a may 29, 2008 ac electrical characteristics table 5. 0.7v differential ac characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c note 1: this parameter is defined in accordance with jedec standard 65. note 2: defined as skew within a bank of outputs at the same voltage and with equal load conditions. parameter symbol test conditio ns minimum typical maximum units f max output frequency 98 160 mhz t jit(cc) cycle-to-cycle jitter; note 1 35 ps t sk(b) bank skew, note 2 30 ps v high output voltage high qbx/nqbx 530 870 mv v low output voltage low qbx/nqbx -150 mv v ovs max. voltage, overshoot qbx/nqbx v high + 0.35 v v uds min. voltage, undershoot qbx/nqbx -0.3 v v rb ringback voltage qbx/nqbx 0.2 v v cross absolute crossing voltage qbx/nqbx @ 0.7v swing 250 550 mv ? v cross total variation of v cross over all edges qbx/nqbx @ 0.7v swing 140 mv t r / t f output rise/fall time qbx/nqbx measured between 0.175v to 0.525v 175 700 ps qax/nqax 20% to 80% 250 600 ps ? t r / ? t f rise/fall time variation qbx/nqbx 125 ps t rfm rise/fall matching qbx/nqbx 20 % odc output duty cycle 48 52 %
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 7 ics8741004bgi rev. a may 29, 2008 parameter measureme nt information 3.3v hcsl output load ac test circuit differential input level cycle-to-cycle jitter 3.3v lvds output load ac test circuit bank skew lvds output duty cycle/pulse width/period r ref = 475 ? measurement point 33 ? 50 ? 50 ? 33 ? measurement point 49.9 ? 49.9 ? hcsl gnd 2pf 2pf 0v v dda v dd, v ddo 3.3v5% 3.3v5% nclk clk v dd gnd v os cross points v od ? ? ? ? cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nqa[0:1], nqb[0:1] qa[0:1], qb[0:1] scope qx nqx 3.3v5% power supply +? float gnd lvds v dda v dd, v ddo t sk(b) nqx0 qx0 nqx1 qx1 where x is either bank a or bank b t pw t period t pw t period odc = x 100% nqa[0:1], nqb[0:1] qa[0:1], qb[0:1]
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 8 ics8741004bgi rev. a may 29, 2008 parameter measurement in formation, continued lvds output rise/fall time differential output voltage setup differential measurement points for duty cycle/period offset voltage setup differential measurement points for ringback hcsl differential measurement points for rise/fall time clock outputs 20% 80% 80% 20% t r t f v od ? ? ? 100 out out lvds dc input v od / ? v od v dd clock period (differential) positive duty cycle (differential) negative duty cycle (differential) q - nq 0.0v out out lvds dc input ? ? ? v os / ? v os v dd t st able t stable v rb v rb q - nq -150mv v rb = -100mv v rb = +100mv +150mv 0.0v q - nq -150mv +150mv 0.0v fall edge rate rise edge rate
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 9 ics8741004bgi rev. a may 29, 2008 parameter measurement in formation, continued single-ended measurement points for delta cross point differential measurement points for duty cycle/period differential measurement points for rise/fall matching q nq v cross_delta = 140mv clock period (differential) positive duty cycle (differential) negative duty cycle (differential) q - nq 0.0v nq q v cross _ median nq q v cross _ median v cross _ median +75mv v cross _ median -75mv t fall t rise
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 10 ics8741004bgi rev. a may 29, 2008 application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolati on is required. the ics8741004i provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd, v dda and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering wiring the differential input to accept single ended levels figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possib le to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 2. single-ende d signal driving differential input v dd v dda 3.3v 10 ? 10f .01f .01f v_ref single ended clock input v dd clk nclk r1 1k c1 0.1u r2 1k
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 11 ics8741004bgi rev. a may 29, 2008 differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. hiperclocks clk/nclk input driven by an idt open emitter hiperclocks lvhstl driver figure 3c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 3e. hiperclocks clk/nclk input driven by a 3.3v hcsl driver figure 3b. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 3d. hiperclocks clk/nclk input driven by a 3.3v lvds driver figure 3f. hiperclocks clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt hiperclocks lvhstl driver hiperclocks input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl hiperclocks input hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 ? zo = 50 ? hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 ? clk nclk hiperclocks input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? clk nclk hiperclocks sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 12 ics8741004bgi rev. a may 29, 2008 recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: differential outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached. lvds driver termination a general lvds interface is shown in figure 4. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. figure 4. typical lvds driver termination 3.3v lvds driver r1 100 ? ? + 3.3v 50 ? 50 ? 100 ? differential transmission line
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 13 ics8741004bgi rev. a may 29, 2008 recommended termination figure 5a is the recommended termination for applications which require the receiver and driver to be on a separate pcb. all traces should be 50 ? impedance. figure 5a. recommended termination figure 5b is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same pcb. all traces should all be 50 ? impedance. figure 5b. recommended termination
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 14 ics8741004bgi rev. a may 29, 2008 epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadfame base package, amkor technology. figure 6. assembly for exposed pad thermal rel ease path - side view (drawing not to scale) ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 15 ics8741004bgi rev. a may 29, 2008 schematic example figure 7 shows an example of ics8741004i application schematic. in this example, the device is operated at v dd = v ddo = 3.3v. two examples of lvds terminations and two examples of hcsl terminations are shown in this schematic. the input is driven by a 3.3v lvpecl driver. the decoupling capacitors should be located as close as possible to the power pin. figure 7. ics8741004i schematic example qa0 to logic input pins tl4 zo = 50 + - c5 .1uf r1 100 vddo=3.3v vdd c2 10uf c1 0.1uf oeb c3 0.01u to logic input pins r3 50 zo = 50 ohm recommended for pci express add-in card vddo r7 33 u1 ics8741004i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 /qa1 qa1 vddo qa0 /qa0 mr bw_sel nc vdda f_sela vdd oea clk /clk gnd gnd oeb f_selb iref /qb0 qb0 vddo qb1 /qb1 /qa0 r10 50 lvpecl driv er logic control input examples ru2 not install r6 33 qa0 /qa0 c4 0.1u /qb0 r11 50 qb0 r9 50 f_sela zo = 50 ohm set logic input to '1' (u1:22) vddo /qb0 qa1 r12 50 r14 50 tl8 zo = 50 /qb1 alternate lvds termination + - zo = 50 ohm /qa1 bw_sel oea rd2 1k rd1 not install recommended for pci express point-to-point connection qb0 nclk clk zo = 50 ohm f_selb vddo vdd = 3.3v zo = 50 ohm vdd zo = 50 ohm r2 50 r13 50 tl9 zo = 50 hcsl termination r8 50 c6 .1uf + - set logic input to '0' (u1:3) ru1 1k qb1 r4 10 mr tl6 zo = 50 vdd=3.3v r5 475 + -
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 16 ics8741004bgi rev. a may 29, 2008 power considerations this section provides information on power dissipa tion and junction temperature for the ics8741004i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics741004i is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (45ma + 12ma) = 197.5mw power (lvds_output) max = v ddo_max * i ddo_max = 3.465v * 80ma = 277.2mw power (hcsl_output) max = 44.5mw * 2 = 89mw total power_ max = (3.465v, with all outputs switchin g) = 197.5mw + 277.2mw + 89mw = 563.7mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 32.1c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.564w * 32.1c/w = 103.1c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 6. thermal resistance ja for 24 lead tssop, e-pad, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 32.1c/w 25.5c/w 24.0c/w
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 17 ics8741004bgi rev. a may 29, 2008 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 8. figure 8. hcsl driver circuit and termination hcsl is a current steering output which s ources a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 ? load to ground. the highest power dissipation occurs when v dd _ max . power = (v dd_max ? v out ) * i out , since v out ? i out * r l = (v dd_max ? i out * r l ) * i out = (3.465v ? 17ma * 50 ? ) * 17ma total power dissipation per output pair = 44.5mw v dd v out r l 50 ? ic i out = 17ma r ref = 475 ? 1%
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 18 ics8741004bgi rev. a may 29, 2008 reliability information table 7. ja vs. air flow table for a 24 lead tssop, e-pad transistor count the transistor count for ics8741004i is: 1318 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 32.1c/w 25.5c/w 24.0c/w
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 19 ics8741004bgi rev. a may 29, 2008 package outline and package dimension package outline - g suffix for 24 lead tssop, e-pad table 8. package dimensions all dimensions in millimeters symbol minimum nominal maximum n 24 a 1.10 a1 0.05 0.15 a2 0.85 0.90 0.95 b 0.19 0.30 b1 0.19 0.22 0.25 c 0.09 0.20 c1 0.09 0.127 0.16 d 7.70 7.90 e 6.40 basic e1 4.30 4.40 4.50 e 0.65 basic l 0.50 0.60 0.70 p 5.0 5.5 p1 3.0 3.2 0 8 0.076 bbb 0.10
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 20 ics8741004bgi rev. a may 29, 2008 ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8741004bgi ics8741004bgi 24 lead tssop, e-pad tray -40 c to 85 c 8741004bgit ics8741004bgi 24 lead tssop, e-pad 2500 tape & reel -40 c to 85 c 8741004BGILF ics8741004bil ?lead-free? 24 lead tssop, e-pad tray -40 c to 85 c 8741004BGILFt ics8741004bil ?lead-free? 24 lead tssop, e-pad 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support device s or critical medical instruments.
ics8741004i differential-to-lvds/0.7v differen tial pci express? jitter attenuator idt? / ics? pci express? jitter attenuator 21 ics8741004bgi rev. a may 29, 2008 revision history sheet rev table page description of change date a t3c 4 16 & 17 added f_sel function table. power considerations - updated power dissi pation section to coincide with updates to the calculations & equations section on page 17. 5/29/08
ics871004i differential-to-lvds/0.7 v differential pci expr ess? jitter attenuator www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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